1. Field of the Invention
The invention relates generally to a clock scheme in a digital circuit and, more particularly, to a dynamic duty-cycle correction scheme using a single-edge clock adjustment technique.
2. Description of the Related Art
Some high-speed circuit techniques in digital-circuit design, such as separated-latch design, render chip performance sensitive to clock duty cycle. That is, duty cycle sometimes improves or degrades maximum chip frequency. Whether a particular asymmetry yields an improvement or degradation is a function of the asymmetry type and the critical timing path. The asymmetry type, for example, is determined by whether the clock remains at a logical 1 longer than a logical 0, or vice versa. If reversible, a particular clock asymmetry that results in chip performance degradation can yield a performance improvement when reversed.
The ideal clock distribution, therefore, should permit fine adjustments for the clock duty cycle via either primary input control or BIOS control bits. Furthermore, these adjustments should be invariant to changes in process, temperature, and supply voltage. For example, settings on a first chip that yield a 10-picosecond adjustment should yield the same 10-picosecond adjustment on a second chip regardless of temperature, process, and supply voltage of the second chip.
Because this degree of invariance is only achievable via active feedback control, another design restriction has to be mentioned. The active feedback loop employed in the duty cycle correction circuit should not interfere with the feedback loop employed in a phase-locked loop (PLL). At best, such interference between the two feedback loops would increase clock jitter. At worst, such interference might render one or both circuits unstable.
Therefore, there is a need for a mechanism that permits fine adjustments of the clock duty cycle, achieves the desired invariance to process, temperature, and supply voltage, and does not interfere with the operation of the PLL.
A duty cycle correction circuit has a delay-control circuit coupled to a clock-inverter circuit. The delay-control circuit includes first and second voltage dividers coupled to a differential amplifier coupled to a stability circuit. The first voltage divider receives a first clock signal. The first and second voltage dividers generate first and second output voltage, respectively. The differential amplifier has first and second input terminals coupled to the first and second output voltages, respectively, and outputs a third output voltage. The stability circuit receives the third output voltage and outputs a delay-control voltage. The clock inverter circuit receives a second clock signal and is coupled to the delay-control voltage. The delay-control voltage has first, second, third, and fourth field effect transistors (FETs).
The first FET has a source, a gate, and a drain. The gate of the first FET is coupled to the delay-control voltage, and the source of the first FET is coupled to the first bias voltage.
The second FET has a source, a gate, and a drain. The source of the second FET is coupled to the first bias voltage. The gate of the second FET receives the second clock signal, and the drain of the second FET outputs the third clock signal.
The third FET has a source, a gate, and a drain. The source of the third FET is coupled to the drain of the first FET, and the gate of the third FET is coupled to the gate of the second FET. The drain of the third FET is coupled to the drain of the second FET.
The fourth FET has a source, a gate, and a drain. The source of the fourth FET is coupled to the second bias voltage, and the gate of the fourth FET is coupled to the gates of the second and third FETs. The drain of the fourth FET is coupled to the drains of the second and third FETs.